The field of the invention relates to a method and mechanism for calculating and comparing the resistance values for networks of resistors.
It is often desirable for circuit designers to be able to view/visualize networks of resistors as a single equivalent resistance value. For example, in order for analog designers to compare the resistances of networks of resistors and to enable the identification of “hot spots” of resistance, it is useful to reduce the resistive complexity of their designs, which may consist of both resistors added by the designers as well as the large number of resistors introduced as a by-product of IC physical layout and extraction of the design. In the case of parasitic extraction, a single net as entered in the schematic design is transformed into a network of parasitic resistors. In order to visualize/compare these post-extraction networks, it can be necessary to collapse these networks into single equivalent resistors.
For a network of resistors with two external terminals, this single equivalent resistance is the resistance between one external terminal and the other, which can be obtained using Ohm's law, or other techniques such as topological, or mathematical reduction. In the case of topological reduction, using traditional reduction via series parallel, and delta-star transformations, there is no single solution for a multi-terminal net, since these reductions are based on transformations for two-terminal networks. Using this technique on a multi-terminal network, can reduce the number of resistors, but will still result in a network of resistors, typically a resistor between each terminal pair. As such, while these approaches may reduce the number of resistors in the circuit, they do not reduce the number of terminals on the network, subsequently preventing them from being used to arrive at a single resistance value for the network.
Existing research and implementations of topological and mathematical network reducers are aimed at reducing the complexity of the resistance network for simulation purposes, not for visualization or comparison purposes. The main limitation of mathematical reduction techniques is that they do not remove any external terminals of the network. There have been proposed reducers which do discard external terminals, but these do this by shorting terminals together that do not affect the accuracy of the results significantly. In order to reduce to a single resistor, one would have to accept a very low accuracy result.
To address these and other problems with prior solutions, embodiments of the invention describe a technique, and implementation for arriving at such a single value for the effective resistance for a network of resistors, irrespective of the number of external terminals. An aspect of an embodiment comprises the reduction of any network of resistors to a single resistance value. Another aspect comprises the application of the power loss calculation to determine the effective resistance. Yet another aspect comprises integration of the method/mechanism with an analog simulator
Further details of aspects, objects, and advantages of the invention are described below in the detailed description, drawings, and claims. Both the foregoing general description and the following detailed description are exemplary and explanatory, and are not intended to be limiting as to the scope of the invention.